PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 92

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

Operational Mode Status bits in the data RAM:
Address:see memory map
RxSTA(1:0)
FECV
SLIP
FSYNC *
FCV *
MSYNC / LD *
Note: with * marked bits are not evaluated by the DELIC, only for VIP testing.
Data Sheet
7
x
Bits SLIP, FECV and are directly available to the DSP software in the TRANSIU
receive data RAM.
MSYNC
6
Receiver Status Change (S/T, U
00 = Receiver is not synchronized to the line; no signal on line
01 = Level detected on line (any signal) (INF 1 in LT-S mode)
10 = Receiver is synchronized to the line, but not activated
11 = Receiver is synchronized and activated (INFO 4 for LT-T mode
INFO 3 for LT-S and U
Far-end Code Violation (S/T, U
0 = Normal operation
1 = Illegal code: FECV according to ANSI T1.605 detected (S/T)
Frame Slip Detected (LT-T)
0 = No frame slip detected
1 = A frame slip of more than 20 µs was detected on the LT-T channel
F-Bit Synchronous (S/T + U
Code Violation in F-Bit detected (U
Multiframe Synchronous (U
(INFO 2 in LT-T mode)
(INFO 0)
FCV
5
FSYNC
data byte 1
data byte 2
data byte 3
4
PN
75
)
PN
PN
), Level Detected (S/T), test mode!
test mode only!)
PN
SLIP
PN
3
)
PN
)
test mode only!)
FECV
2
Functional Description
RxSTA(1:0)
1
PEB 20570
PEB 20571
2003-07-31
0