PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 126

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

4.4.1.7
There are eight 16-bit tri-state control registers in the PCMU. Each bit determines
whether its associated time slot is valid or invalid.
• '0' = the controlled time slot is invalid
• '1' = the controlled time slot is valid
The tri-state bits control the data transmit pins TXD0 - TXD3.
A special set/reset write method is used for updating the tri-state control registers. Every
tri-state control register is mapped to 2 addresses: the first is used for set operation, the
second for reset operation. Both addresses may be used for read operation.
• Set operation: This operation is executed during DSP write access to the set address
• Reset operation: This operation is executed during DSP write access to the reset
The Tri-state Control Registers (PTS0-7) can be accessed by the DSP. Every bit of them
controls the TSC signal of one of the 4 PCM ports, for one time slot. The time slot and
the port controlled by every bit depend on the data rate mode. In 1 x 256 TS/frame, it
depends also on the selected half of the frame. Each TSC signals controls directly its
respective TxD port, and is also driven outward via the corresponding TSCn output pin.
For the 4 x 32 time slot per frame mode, the next table depicts which port is controlled
by each TSC register, and during which time slot. Bit 0 of each TSC register controls the
first time slot of the listed time slot range, bit 1 controls the second one etc.
Table 37
Time Slots
0..15
16..31
In 2 x 64 time slot per frame mode, only PCM ports 0 and 2 are used. TSC1 and TSC3
are permanently '0' (all time slots are invalid).
Table 38
Time Slots
0..15
16..31
32..47
48..63
Data Sheet
of one of the TSC registers. The bits in the TSC register are set to '1' according to the
bits in the written word. The other bits maintain their value.
address of one of the TSC registers. The bits in the TSC register are reset to '0'
according to the bits in the written word. The other bits maintain their value.
PCMU Tri-state Control Logic
PTSC0
PTSC1
PTSC2
PTSC3
PTSC0
PTSC1
PCM TSC in 4 x 32 TS Mode (4 x 2 MBit/s)
PCM TSC in 2 x 64 TS Mode (2 x 4MBit/s)
TSC0
TSC0
inactive
inactive
inactive
inactive
PTSC2
PTSC3
TSC1
TSC1
109
PTSC4
PTSC5
PTSC6
PTSC7
PTSC4
PTSC5
TSC2
TSC2
Functional Description
inactive
inactive
inactive
inactive
PTSC6
PTSC7
PEB 20570
PEB 20571
TSC3
TSC3
2003-07-31