PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 153

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

Figure 54
1. The DMA transmit mailbox is empty
2. DELIC requests DMA service via DREQT
3. The DMA controller addresses memory with ADDR and the DELIC with DACK
4. With read signal (RD), memory data reach the data bus
5. In parallel, when the data are stable on the bus, the DMA controller writes it directly
Note: In Intel/Infineon Mode, RD is used as write signal for the transmit mailbox.
4.10.1
In transactions between DMA controller and DELIC, the DELIC indicates that it is ready
to transmit/ receive data by setting DREQT / DREQR high. The DMA controller answers
by driving DACK low. DACK acts like a CS and remains low during the entire transaction.
By driving DACK high, the DMA controller can stop the transaction on any stage, even if
the data transfer has not been finished yet.
DELIC Programming
1. Set the DMA transfer mode in MCFG register by the P to Memory-to-Memory or Fly-
Data Sheet
into the transmit mailbox.
by mode.
DMA Handshake
Single cycle DMA transfer mode for Transmit Data
1-Cycle-Mode-T
Controller
DMA
DREQT
ADDR
136
DACK
+ RD
RD
Memory
Mailbox
DELIC
DMA
Data
Data Bus
Functional Description
PEB 20570
PEB 20571
2003-07-31