PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 85

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

EXTEST is used to verify the board interconnections.
When the TAP controller is in the state “update DR”, all output pins are updated with the
falling edge of JTCK. When it has entered state “capture DR” the levels of all input pins
are latched with the rising edge of JTCK. The in/out shifting of the scan vectors is
typically done using the instruction SAMPLE/PRELOAD.
INTEST supports internal chip testing.
When the TAP controller is in the state “update DR”, all inputs are updated internally with
the falling edge of JTCK. When it has entered state “capture DR” the levels of all outputs
are latched with the rising edge of JTCK. The in/out shifting of the scan vectors is
typically done using the instruction SAMPLE/PRELOAD.
Note: 0011 (IDCODE) is the default value of the instruction register.
SAMPLE/PRELOAD provides a snap-shot of the pin level during normal operation or is
used to either preload (TDI) or shift out (TDO) the boundary scan test vector. Both
activities are transparent to the system functionality.
IDCODE
The 32-bit identification register is serially read out via TDO. It contains the version
number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB
is fixed to ’1’. The code for the DELIC version 3.1 is ’0100’.
Note: In the state “test logic reset” the code “0011” is loaded into the instruction code
BYPASS, a bit entering TDI is shifted to TDO after one JTCK clock cycle, e.g. to skip
testing of selected ICs on a printed circuit board.
Data Sheet
Version
0100
register.
Device Code
0000 0000 0101 0111
68
Manufacturer Code
0000 1000 001
Interface Description
1
PEB 20570
PEB 20571
2003-07-31
Output
--> TDO