PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 194

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

6.2.2
6.2.2.1
ICR Register
Reset value: 02
ICDB
A
OD
DC
DR(1:0)
Data Sheet
15
x
7
x
IOMU Register Description
IOMU Control Register
Idle Current D-Buffer (for test purpose; only if IOMU is in idle mode: ICR:A
= ’0’)
0 =
1 =
IOMU Activation
0 =
1 =
DD0 and DD1 Output Mode
0 =
1 =
Double Data Rate Clock
0 =
1 =
IOM-2 Data Rate
00 =
01 =
10 =
11 =
H
14
x
6
x
Make frame buffer 0 accessible to the DSP
Make frame buffer 1 accessible to the DSP
The IOMU is Idle. The state machine of the IOMU is idle, and no
accesses to the I-buffer are executed by the IOMU.
The IOMU is active, and works according to the programming of the
other Control Register bits.
Push-Pull mode.
Open-Drain mode
Single clock (DCL frequency is identical to the IOM-2 data rate)
Double clock (DCL frequency is double the IOM-2 data rate)
IOM-2 data rate of 1 x 384 kbit/s (1 x 6 time slots/frame)
IOM-2 data rate of 1 x 768 kbit/s (1 x 12 time slots/frame)
IOM-2 data rate of 2 x 2.048 Mbit/s (2 x 32 time slots/frame)
(default)
IOM-2 data rate of 1 x 4.096 Mbit/s (1 x 64 time slots/frame)
ICDB
13
5
x
12
A
4
x
read/write
177
OD
11
x
3
DC
10
x
2
Register Description
Address: D040
9
1
x
DR(1:0)
PEB 20570
PEB 20571
2003-07-31
8
0
x
H