PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 158

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

4. The DMA controller asserts DACK and issues (Rc_Num+1) read transactions from the
5. DREQR is deasserted (“high” or “low”).
6. If RMSK bit in DINSTA is inactive (“1”), the DMA interrupt to OAK (INT0) is activated.
Note: The OAK must not write to the register DRXCNT while the previous DMA receive
4.10.5
The FIFO size is 16 bytes (8 words) each (Transmit, Receive). On the OAK side, each
of the 8 data registers (TDT0-7 and RDT0-7) can be accessed separately. On the DMA
controller side, only the current top of FIFO is accessible.
Note: The Transmit FIFO and the Receive FIFO are functioning as explained above only
Data Sheet
receive mailbox (“FIFO”).
transaction has not been finished. (The OAK waits for Receive DMA Interrupt and
tests if DTXCNT equals ’F
when the mailbox is in DMA mode (MCFG:DMA = ‘1’). In case of non-DMA mode
(MCFG:DMA = ‘0’) the FIFOs are used as secondary (extension) to the general
mailbox, which means that the general mailbox will have 16 words for each
direction (OAK and
FIFO Access
P
), instead of 8.
H
’.)
141
Functional Description
PEB 20570
PEB 20571
2003-07-31