PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 269

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

Figure 60
Note: R/W is described in Normal mode. In Fly-by mode, R/W should be low during DMA
8.6.1.2
In this mode R and W are used for timing the access and to determine whether it’s a
DMA-read cycle or DMA-write cycle. R and W input signals are used in opposite ways in
Normal mode and in Fly-By mode. The next table details the way in which R and W
should be used in each mode, during DMA transactions:
Data Sheet
DS
DACK
R/W
D
DREQR
read transactions.
DMA Access Timing In Intel/Infineon Mode
DMA Read-Transaction Timing in Motorola Mode
t
t
SRWS
SAS
t
WS
Electrical Characteristics and Timing Diagrams
252
t
t
HSA
t
WS
HSRW
t
last byte
DSDV
t
DSR
t
DSDT
PEB 20570
PEB 20571
2003-07-31