PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 286

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

Note: Usually DSP-clock is generated internally by the internal PLL, in a frequency of
Figure 79
Table 79
Parameter
PDC Minimum High Pulse
PDC Minimum Low Pulse
Note: The Minimum pulse width (high or low) of PDC depends on the DSP clock
Figure 80
Data Sheet
PDC
PDC
61.44 MHz. If on the other hand a lower frequency clcok is provided via CLK_DSP
input pin, the frequency of PDC (input or output) should not exceed the frequency
of DSP-clock-frequency / 4 (DSP clcok frequency devided by 4), in order to
guarantee a proper operation of the DELIC.
frequency. Usually this clock is generated internally by the internal PLL, in a
frequency of 61.44 MHz. In this case the values in the table above are valid. If a
lower frequency for DSP-clock is provided via CLK_DSP input pin, and PDC is
used as input, the low/high pulse width of PDC should not be smaller then
1.5 X DSP-clock-cycle (DSP-clock-cycle is the cycle time of the provided DSP
clock).
PDC Parameters
PDC Timing in Input Mode
PDC Timing in Input Mode
t
PML
Symbol
t
t
PMH
PML
Electrical Characteristics and Timing Diagrams
min.
22
22
269
Limit Values
t
typ.
PCP
max.
t
PMH
Unit Notes
ns
ns
In Input Mode
In Input Mode
PEB 20570
PEB 20571
2003-07-31