PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 292

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

Table 83
Parameter
LCLK0..3 Clock Period
LCLK0..3 Duty Cycle in
output mode
Note: LCLK0..3 are generated with a 50% duty cycle. Even though all LCLKs (0, 1, 2, 3)
Figure 84
Table 84
Parameter
LCLK0..3 Minimum High
Pulse
LCLK0..3 Minimum Low
Pulse
Data Sheet
LCLK0..3
might be operated in all possible frequencies, the frequency of each one of these
clocks should be configured in accordance with the GHDLCU operating mode. For
more detailes see section 6.2.6.2 “GHDLC Channel Mode Register”. Usually DSP-
clock is generated internally by the internal PLL, in a frequency of 61.44 MHz. If
on the other hand a lower frequency clcok is provided via CLK_DSP input pin, the
frequency of LCLK0..3 (input or output) should not exceed the frequency of DSP-
clock-frequency / 4 (DSP clcok frequency devided by 4), in order to guarantee a
proper operation of the DELIC.
LCLK0..3 Timing in Output Mode
LCLK0..3 Timing in Output Mode
LCLK0..3 Timing in Input Mode
Symb
ol
t
LCP
Symbo
l
t
t
LMH
LML
t
LCP
Electrical Characteristics and Timing Diagrams
min.
48
min.
22
22
Limit Values
Limit Values
275
typ.
488
244
122
61
typ.
max.
52
max.
Unit Notes
ns
ns
ns
ns
%
Unit Notes
ns
ns
LCLK0..3 = 2048 kHz
LCLK0..3 = 4096 kHz
LCLK0..3 = 8192 kHz
LCLK0..3 = 16384 kH
z
In Input Mode
In Input Mode
PEB 20570
PEB 20571
2003-07-31