PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 120

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

4.3.2.9
The DRDY input is used when connecting an Infineon QUAT-S transceiver to the DELIC
via the IOM-2 interface. It is driven by the QUAT-S to inform the DELIC when a D-
channel is occupied by another S-interface device.
The IOMU supports the synchronous DRDY mode, i.e. the QUAT-S is operated in LT-T
mode. In this mode, the DRDY signal is valid only during the D-channels.
DRDY = ‘0’ means STOP (ABORT HDLC message), and DRDY = ‘1’ means GO.
Figure 39
IOMU DRDY support features:
• Sampling DRDY only once every D-channel at the first bit.
• Sampling with the first DCL falling edge (in single data-rate DCL mode) or with the
• DRDY support via IOM-2 port 0 only (with a constant delay of one 8 kHz frame)
• The status of the DRDY line can be read from register IDRDYR
Figure 40
Note: If DRDY is not used, DRDY has to be set to ’high’.
Data Sheet
second falling DCL edge (in double data-rate DCL mode), refer to
FSC
DU0
DRDY
Double
Data-Rate DCL
Single
Data-Rate DCL
B1 B2
Support of DRDY Signal from QUAT-S
DRDY
DU0
DRDY Signal Behavior
DRDY Sampling Timing
IOM-2 ch 7
MON
= not valid
go
D
B1 B2
IOM-2 ch 0
MON
stop
D
First bit of
a D-channel
D0
B1 B2
103
Sample point of DRDY
in single data-rate DCL mode
IOM-2 ch 1
valid
Sample point of DRDY
in double data-rate DCL mode
MON
stop
D
second bit of
a D-channel
D1
B1 B2
IOM-2 ch 2
MON
Functional Description
go
D
B1 B2
Figure
IOM-2 ch 3
PEB 20570
PEB 20571
MON
40.
2003-07-31
stop
D