PEB20571FV31XP Infineon Technologies, PEB20571FV31XP Datasheet - Page 270

• Manufacturer Part Number: PEB20571FV31XP
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XP

• Lead Free Status / Rohs Status: Compliant

Table 65
Mode
Normal (Non-Fly-By)
Fly-By
In Fly-By mode R and W are used inverted, because these signals are required also for
concurrent accessing of an external memory device.
Table 66
Parameter
DACK setup time to W or R
falling edge
DACK hold time after W or R
rising edge
D-bus setup time to W rising
edge
D-bus hold time after W
rising edge
DREQT/DREQR delay after
W or R falling edge
W pulse width and interval
between W pulses
R pulse width and interval
between R pulses
D-bus valid after R falling
edge
D-bus float (high impedance)
after R rising edge
Data Sheet
R/W Behavior During DMA Transactions in Normal and in Fly-By
Modes
DMA Transaction Timing in Intel/Infineon Mode
R = ‘1’, W = ‘0’
Write DMA transaction.
(A response to DMA
transmitter request)
Read DMA transaction.
(A response to DMA
receiver request)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
SAW
SAR
HWA
HRA
SDW
HWD
DWR
DRR
WW
WR
DRDV
DRDT
Electrical Characteristics and Timing Diagrams
min.
7
5
5
8
0
30
30
0
0
253
Limit Values
R = ‘0’, W = ‘1’
Read DMA transaction.
(A response to DMA receiver
request)
Write DMA transaction.
(A response to DMA transmitter
request)
max.
36
22
15
Unit
ns
ns
ns
ns
ns
ns
ns
Test
Conditions
Output load
capacity of
50 pF
PEB 20570
PEB 20571
2003-07-31