st72324bk STMicroelectronics, st72324bk Datasheet - Page 98

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

On-chip peripherals
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Bit 5 = SPR2 Divider Enable.
This bit has no effect in slave mode.
Bit 4 = MSTR Master Mode.
Bit 3 = CPOL Clock Polarity.
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Bit 2 = CPHA Clock Phase.
The slave must have the same CPOL and CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial Clock Frequency.
These 2 bits have no effect in slave mode.
Table 46.
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to
0: Divider by 2 enabled
1: Divider by 2 disabled
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS=0 (see
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are reversed.
This bit is set and cleared by software. This bit determines the idle state of the serial
Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
These bits are set and cleared by software. Used with the SPR2 bit, they select the
baud rate of the SPI serial clock SCK output by the SPI in master mode.
SPI master mode SCK frequency
Serial clock
f
f
f
f
CPU
f
f
CPU
CPU
CPU
CPU
CPU
/128
/16
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Section : Master mode fault
SPR2
Table
1
0
0
1
0
0
(MODF)).
46.
SPR1
0
0
0
1
1
1
ST72323 ST72323L
SPR0
0
0
1
0
0
1