st72324bk STMicroelectronics, st72324bk Datasheet - Page 45

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

ST72323 ST72323L
7.4.2
Figure 21. Active-Halt timing overview
Figure 22. Active-Halt mode flowchart
1. This delay occurs only if the MCU exits Active-Halt mode by means of a Reset.
2. Peripheral clocked with an external clock source can still be active.
3. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from Active-Halt mode (such
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘Halt’ instruction when the OIE bit of the Main Clock Controller Status register
(MCCSR) is cleared (see
The MCU can exit Halt mode on reception of either a specific interrupt (see
Interrupt mapping on page
an interrupt, the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is
used to stabilize the oscillator. After the start up delay, the CPU resumes operation by
servicing the interrupt or by fetching the reset vector which woke it up (see
When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
as external interrupt). Refer to
set to the current software priority level of the interrupt routine and restored when the CC register is
popped.
N
[MCCSR.OIE=1]
(MCCSR.OIE=1)
Run
Halt instruction
Instruction
Section 9.2 on page 61
36) or a Reset. When exiting Halt mode by means of a Reset or
Halt
Table 9: Interrupt mapping on page 36
Interrupt
Active
Y
Halt
(3)
256 or 4096 CPU
cycle delay
interrupt
Reset
or
Oscillator
Peripherals
CPU
Oscillator
Peripherals
CPU
I[1:0] bits
I[1:0] bits
N
256 or 4096 CPU clock
for more details on the MCCSR register).
1)
cycle delay
Y
Reset
vector
Fetch
(2)
for more details.
Run
XX
OFF
OFF
OFF
ON
ON
ON
10
4)
Power saving modes
Figure
Table 9:
24).
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