st72324bk STMicroelectronics, st72324bk Datasheet - Page 19

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

ST72323 ST72323L
Table 2.
Address
002Eh to
0012h to
002Ch
002Dh
003Ch
003Dh
000Fh
002Ah
002Bh
003Ah
003Bh
003Eh
003Fh
0010h
0011h
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
0040h
WATCHDOG WDGCR
TIMER A
Port F
Hardware register map
Block
MCC
SPI
ITC
(3)
Register label
PFDR
PFDDR
PFOR
SPIDR
SPICR
SPICSR
ISPR0
ISPR1
ISPR2
ISPR3
EICR
MCCSR
MCCBCR
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
(1)
Port F Data Register
Port F Data Direction Register
Port F Option Register
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
Watchdog Control Register
Main Clock Control / Status Register
Main Clock Controller: Beep Control Register
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
External Interrupt Control Register
(continued)
Reserved area (15 bytes)
Reserved area (3 bytes)
Reserved Area (1 Byte)
Reserved Area (1 byte)
Reserved area (1 byte)
Register name
Register and memory map
Reset status
xxxx x0xxb
00h
FCh
FCh
FFh
FFh
FFh
FFh
FFh
FFh
00h
00h
00h
00h
7Fh
00h
00h
00h
00h
80h
00h
80h
00h
xxh
0xh
xxh
xxh
xxh
xxh
(2)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
Remarks
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