st72324bk STMicroelectronics, st72324bk Datasheet - Page 100

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

On-chip peripherals
Note:
Caution:
100/167
1
2
Bit 1 = SSM SS Management.
Bit 0 = SSI SS Internal Mode.
Data I/O register (SPIDR)
Reset value: undefined
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
A write to the SPIDR register places data directly into the shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see
Table 47.
Address
0021h
0022h
0023h
(hex.)
D7
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See
management.
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin free
for general-purpose I/O)
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of
the SS slave select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected
7
SPIDR
reset value
SPICR
reset value
SPICSR
reset value
Register
SPI register map and reset values
label
D6
Figure
SPIE
MSB
SPIF
7
x
0
0
D5
44).
WCOL
SPE
6
x
0
0
D4
Read/write
SPR2
OVR
5
x
0
0
MODF
MSTR
D3
4
x
0
0
CPOL
Section : Slave select
3
x
x
0
D2
CPHA
SOD
2
x
x
0
ST72323 ST72323L
D1
SPR1
SSM
1
x
x
0
D0
SPR0
0
LSB
SSI
0
x
x
0