st72324bk STMicroelectronics, st72324bk Datasheet - Page 154

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

ST72323 device configuration and ordering information
Note:
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OPT0 = FMP_R Flash memory read-out protection
Option byte 1
OPT7 = PKG1 Pin package selection bit
Table 92.
On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input
pull-up configuration after reset. The configuration of these pads must be kept at reset state
to avoid added current consumption.
OPT6 = RSTC RESET clock cycle selection
OPT5:4 = OSCTYPE[1:0] Oscillator Type
Table 93.
1. The RCosc frequency in ST72F324B Flash devices is centered on 3.5 MHz. (f
OPT3:0 = Reserved, must be kept at default value..
Resonator oscillator
Reserved
Internal RC oscillator
External source
ST72323 devices refer to
Read-out protection, when selected, provides a protection against Program Memory
content extraction and against write access to Flash memory.
Erasing the option bytes when the FMP_R option is selected causes the whole user
memory to be erased first, and the device can be reprogrammed. Refer to the
ST72F324B datasheet and the ST7 Flash Programming Reference Manual for more
details.
0: Read-out protection enabled
1: Read-out protection disabled
This option bit selects the package as shown in
This option bit selects the number of CPU cycles applied during the RESET phase and
when exiting Halt mode. For resonator oscillators, it is advised to select 4096 due to the
long crystal stabilization time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
These option bits select the ST7 main clock source type as shown in
Version
K
J
Package selection (OPT7)
Clock source selection
LQFP48/LQFP44
LQFP32 / SDIP32 / SO34
(1)
Clock source
Section
11.5.2.
Selected package
Table
92.
CPU
1
0
0
1
1
=1.75MHz). For ROM
OSCTYPE
ST72323 ST72323L
Table
PKG1
93.
1
0
0
0
1
0
1