st72324bk STMicroelectronics, st72324bk Datasheet - Page 94

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st72324bk

Manufacturer Part Number
st72324bk
Description
3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
Manufacturer
STMicroelectronics
Datasheet

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On-chip peripherals
9.4.5
94/167
Figure 48. Data clock timing diagram
1. This figure should not be used as a replacement for parametric information. Refer to the
Error flags
Master mode fault (MODF)
Master mode fault occurs when the master device has its SS pin pulled low.
When a Master mode fault occurs:
Clearing the MODF bit is done through a software sequence:
Electrical
(from slave)
(from slave)
(to slave)
(to slave)
(from master)
(from master)
SCK
(CPOL = 0)
MISO
MOSI
CAPTURE STROBE
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
MOSI
Capture strobe
SCK
(CPOL = 1)
SS
SS
The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is
set.
The SPE bit is reset. This blocks all output from the device and disables the SPI
peripheral.
The MSTR bit is reset, thus forcing the device into slave mode.
characteristics.
MSBit
MSBit Bit 6
MSBit Bit 6
MSBit Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Bit 5
CPHA =0
CPHA =1
Bit 4
Bit 4
Bit 4
Bit 4
Bit3
Bit3
Bit3
Bit3
Bit 2
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 1
ST72323 ST72323L
LSBit
LSBit
LSBit
LSBit
Section 11:

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