st72324bk STMicroelectronics, st72324bk Datasheet - Page 165

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st72324bk

Manufacturer Part Number
st72324bk
Description
3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
Manufacturer
STMicroelectronics
Datasheet

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ST72323 ST72323L
14.4
14.4.1
14.4.2
14.5
14.5.1
16-bit timer
PWM mode
In PWM mode, the first PWM pulse is missed after writing the value FFFCh in the OC1R
register (OC1HR, OC1LR). It leads to either full or no PWM during a period, depending on
the OLVL1 and OLVL2 settings.
TIMD set simultaneously with OC interrupt
If the 16-bit timer is disabled at the same time the output compare event occurs then output
compare flag gets locked and cannot be cleared before the timer is enabled again.
Impact on the application: If output compare interrupt is enabled, then the output compare
flag cannot be cleared in the timer interrupt routine. Consequently the interrupt service
routine is called repeatedly and application get stuck which causes the watchdog reset if
enabled by the application.
Workaround
Disable the timer interrupt before disabling the timer. Again while enabling, first enable the
timer then the timer interrupts.
ST72F324B compatible Flash devices
Internal RC operation
In ST72F324J and ST72F324K devices, the internal RC oscillator is centered on a different
frequency from the ST72323L and ST72323 ROM devices.
Perform the following to disable the timer:
Perform the following to enable the timer again:
TACR1 or TBCR1 = 0x00h; // Disable the compare interrupt
TACSR | or TBCSR | = 0x40; // Disable the timer
TACSR & or TBCSR &= ~0x40; // Enable the timer
TACR1 or TBCR1 = 0x40; // Enable the compare interrupt
Known limitations
165/167

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