st72324bk STMicroelectronics, st72324bk Datasheet - Page 44

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

Power saving modes
7.4
7.4.1
Note:
Caution:
44/167
Active-Halt and Halt modes
Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘Halt’ instruction. The decision to enter either in Active-
Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR
register).
Table 15.
Active-Halt mode
Active-Halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘Halt’ instruction when the OIE bit of the Main Clock
Controller Status register (MCCSR) is set (see
the MCCSR register).
The MCU can exit Active-Halt mode on reception of either an MCC/RTC interrupt, a specific
interrupt (see
mode by means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes
operation by servicing the interrupt or by fetching the reset vector which woke it up (see
Figure
When entering Active-Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active-Halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
The safeguard against staying locked in Active-Halt mode is provided by the oscillator
interrupt.
As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),
entering Active-Halt mode while the Watchdog is active does not generate a Reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
When exiting Active-Halt mode following an interrupt, OIE bit of MCCSR register must not
be cleared before t
depending on option byte). Otherwise, the ST7 enters Halt mode for the remaining t
period.
MCCSR OIE bit
22).
0
1
MCC/RTC low-power mode selection
Table 9: Interrupt mapping on page
Halt mode
Active-Halt mode
DELAY
Power saving mode entered when Halt instruction is executed
after the interrupt occurs (t
Section 9.2 on page 61
36) or a Reset. When exiting Active-Halt
DELAY
= 256 or 4096 t
for more details on
ST72323 ST72323L
CPU
delay
DELAY