st72324bk STMicroelectronics, st72324bk Datasheet - Page 96

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

On-chip peripherals
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Single master systems
A typical single master system may be configured, using an MCU as the master and four
MCUs as slaves (see
The master device selects the individual slave devices by using four pins of a parallel port to
control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports will be forced to be
inputs at that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line the master allows only one active slave
device during a transmission.
For more security, the slave device may respond to the master with the received data byte.
Then the master will receive the previous byte back from the slave device if all MISO and
MOSI pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes with
command fields.
Figure 50. Single master / multiple slave configuration
Table 44.
Wait
Halt
5V
Mode
MOSI
SS
No effect on SPI.
SPI interrupt events cause the device to exit from Wait mode.
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by
an interrupt with “exit from Halt mode” capability. The data received is subsequently read
from the SPIDR register when the software is running (interrupt vector fetching). If
several data are received before the wake-up event, then an overrun error is generated.
This error can be detected after the fetch of the interrupt routine that woke up the device.
SCK
SCK
MOSI
Low-power modes
MCU
Master
Slave
MCU
MISO
MISO
SS
Figure
50).
MOSI
SCK
MCU
Slave
MISO
SS
Description
MOSI
SCK
Slave
MCU
MISO
SS
ST72323 ST72323L
MOSI
SCK
MCU
Slave
MISO
SS