st72324bk STMicroelectronics, st72324bk Datasheet - Page 27

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

ST72323 ST72323L
5.2
5.2.1
Caution:
5.2.2
Reset sequence manager (RSM)
Introduction
The reset sequence manager includes three RESET sources as shown in
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●
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic RESET sequence consists of 3 phases as shown in
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●
●
When the ST72323 is unprogrammed or fully erased, the Flash is blank and the RESET
vector is not programmed. For this reason, it is recommended to keep the RESET pin in low
state until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application.
The RESET vector fetch phase duration is 2 clock cycles.
Figure 11. Reset sequence phases
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See
characteristics
A reset signal originating from an external source must have a duration of at least t
in order to be recognized. This detection is asynchronous and therefore the MCU can enter
reset state even in Halt mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in
Electrical
External RESET source pulse
Internal WATCHDOG RESET
Active Phase depending on the RESET source
256 or 4096 CPU clock cycle delay (selected by option byte)
RESET vector fetch
characteristics.
for more details.
Active phase
256 or 4096 clock cycles
Internal reset
Reset
Supply, reset and clock management
Section 11: Electrical
Figure
vector
Fetch
11:
Figure
ON
Section 11:
weak pull-up
12:
h(RSTL)in
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