st72324bk STMicroelectronics, st72324bk Datasheet - Page 90

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

On-chip peripherals
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Figure 45. Single master/ single slave application
Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
●
●
MSBit
8-bit shift register
In Master mode:
–
In Slave Mode:
There are two cases depending on the data/clock timing relationship (see
–
–
generator
clock
SPI
SS internal must be held high continuously
If CPHA=1 (data latched on 2nd clock edge):
SS internal must be held low during the entire transmission. This implies that in
single slave applications the SS pin either can be tied to V
standard I/O by managing the SS function by software (SSM= 1 and SSI=0 in the
in the SPICSR register)
If CPHA=0 (data latched on 1st clock edge):
SS internal must be held low during byte transmission and pulled high between
each byte to allow the slave to write to the shift register. If SS is not pulled high, a
Write Collision error will occur when the slave writes to the shift register (see
Section
Master
).
LSBit
Figure
47)
MOSI
SCK
SS
MISO
+5 V
MISO
MOSI
SCK
SS
8-bit shift register
MSBit
Not used if SS is managed
by software
SS
, or made free for
ST72323 ST72323L
Slave
Figure
LSBit
46):