st72324bk STMicroelectronics, st72324bk Datasheet - Page 95

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

ST72323 ST72323L
Note:
Note:
1
2
1.
2.
To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high
during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their
original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set
except in the MODF bit clearing sequence.
Overrun condition (OVR)
An overrun condition occurs, when the master device has sent a data byte and the slave
device has not cleared the SPIF bit issued from the previously transmitted byte.
When an overrun occurs:
●
In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A
read to the SPIDR register returns this byte. All other bytes are lost.
The OVR bit is cleared by reading the SPICSR register.
Write collision error (WCOL)
A write collision occurs when the software tries to write to the SPIDR register while a data
transfer is taking place with an external device. When this happens, the transfer continues
uninterrupted; and the software write will be unsuccessful.
Write collisions can occur both in master and slave mode. See also
management.
A "read collision" will never occur since the received data byte is placed in a buffer in which
access is always synchronous with the MCU operation.
The WCOL bit in the SPICSR register is set if a write collision occurs. No SPI interrupt is
generated when the WCOL bit is set (the WCOL bit is a status flag only). Clearing the
WCOL bit is done through a software sequence (see
Figure 49. Clearing the WCOL bit (write collision flag) software sequence
1. Writing to the SPIDR register instead of reading it does not reset the WCOL bit.
A read access to the SPICSR register while the MODF bit is set.
A write to the SPICR register.
The OVR bit is set and an interrupt request is generated if the SPIE bit is set.
1st step
2nd step
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st step
2nd step
Read SPICSR
Read SPIDR
Result
SPIF =0
WCOL=0
Read SPIDR
Read SPICSR
Figure
Result
49).
WCOL=0
Section : Slave select
On-chip peripherals
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