st72324bk STMicroelectronics, st72324bk Datasheet - Page 49

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

ST72323 ST72323L
8
8.1
8.2
8.2.1
Note:
1
2
3
I/O ports
Introduction
The I/O ports offer different functional modes:
●
and for specific pins:
●
●
An I/O port contains up to 8 pins. Each pin can be programmed independently as digital
input (with or without interrupt generation) or digital output.
Functional description
Each port has 2 main registers:
●
●
and one optional register:
●
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
registers: bit X corresponding to pin X of the port. The same correspondence is used for the
DR register.
The following description takes into account the OR register, (for specific ports which do not
provide this register refer to the I/O Port Implementation section). The generic I/O block
diagram is shown in
Input modes
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Writing the DR register modifies the latch value but does not affect the pin status.
When switching from input to output mode, the DR register has to be written first to drive the
correct level on the pin as soon as the port is configured as an output.
Do not use read/modify/write instructions (BSET or BRES) to modify the DR register as this
might corrupt the DR content for I/Os configured as input.
External interrupt function
When an I/O is configured as Input with Interrupt, an event on this I/O can generate an
external interrupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is
independently programmable using the sensitivity bits in the EICR register.
transfer of data through digital inputs and outputs
external interrupt generation
alternate signal input/output for the on-chip peripherals.
Data Register (DR)
Data Direction Register (DDR)
Option Register (OR)
Figure 25
I/O ports
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