st72324bk STMicroelectronics, st72324bk Datasheet - Page 136

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st72324bk

Manufacturer Part Number
st72324bk
Description
3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
Manufacturer
STMicroelectronics
Datasheet

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Electrical characteristics
11.9
11.9.1
136/167
Control pin characteristics
Asynchronous RESET pin
Subject to general operating conditions for V
Table 80.
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The I
4. Data guaranteed by design, not tested in production.
5. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses
6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially
t
w(RSTL)out
t
t
Symbol
h(RSTL)in
g(RSTL)in
the sum of I
applied on the RESET pin with a duration below t
in noisy environments.
R
V
V
V
V
I
hys
IO
ON
OL
IH
IL
IO
current sunk must always respect the absolute maximum rating specified in
Input low level voltage
Input high level voltage
Schmitt trigger voltage
hysteresis
Output low level voltage
Driving current on RESET pin
Weak pull-up equivalent
resistor
Generated reset pulse
duration
External reset pulse hold
time
Filtered glitch duration
IO
Asynchronous RESET pin characteristics
(I/O ports and control pins) must not exceed I
(5)
Parameter
(2)
(6)
(1)
(1)
(3)
V
V
Watchdog reset
DD
DD
h(RSTL)in
DD
= 5 V
= 5 V I
Conditions
, f
CPU
can be ignored.
VSS
IO
, and T
= +2 mA
.
A
unless otherwise specified.
0.7V
20
Min
2.5
20
(4)
DD
Section Table 61.
ST72323 ST72323L
Typ
200
2.5
0.2
30
2
0.3V
Max
120
0.5
DD
and
Unit
mA
µs
µs
ns
V

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