st72324bk STMicroelectronics, st72324bk Datasheet - Page 97

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

ST72323 ST72323L
Note:
Caution:
Note:
9.4.6
Using the SPI to wake up the MCU from Halt mode
In slave configuration, the SPI is able to wakeup the ST7 device from Halt mode through an
SPIF interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from Halt mode state to normal
state. If the SPI exits from Slave mode, it returns to normal state immediately.
The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. So if Slave
selection is configured as external (see
on the SS pin when the slave enters Halt mode.
Table 45.
The SPI interrupt events are connected to the same interrupt vector (see
Interrupts).
They generate an interrupt if the corresponding Enable Control bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
Register description
Control register (SPICR)
Reset value: 0000 xxxx (0xh)
Bit 7 = SPIE Serial Peripheral Interrupt Enable.
Bit 6 = SPE Serial Peripheral Output Enable.
SPI end of transfer event
Master mode fault event
Overrun error
SPIE
7
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1, MODF=1 or OVR=1 in the SPICSR
register
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS=0 (see
reset, so the SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Interrupt event
Interrupts
SPE
SPR2
Section : Master mode fault
Event flag
MODF
SPIF
OVR
MSTR
Section
Read/Write
Enable Control
CPOL
), make sure the master drives a low level
SPIE
(MODF)). The SPE bit is cleared by
bit
CPHA
Exit from Wait Exit from Halt
Yes
Yes
Yes
On-chip peripherals
SPR1
Section 6:
Yes
No
No
SPR0
0
97/167