st72324bk STMicroelectronics, st72324bk Datasheet - Page 81

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

ST72323 ST72323L
9.3.7
Register description
Each Timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) relating to the two input captures, the two output compares, the
counter and the alternate counter.
Control register 1 (CR1)
Reset value: 0000 0000 (00h)
Bit 7 = ICIE Input Capture Interrupt Enable.
Bit 6 = OCIE Output Compare Interrupt Enable.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
Bit 4 = FOLV2 Forced Output Compare 2.
Bit 3 = FOLV1 Forced Output Compare 1.
Bit 2 = OLVL2 Output Level 2.
Bit 1 = IEDG1 Input Edge 1.
ICIE
7
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is
set.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even
if there is no successful comparison.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there
is no successful comparison.
This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the
OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1
pin in One Pulse Mode and Pulse Width Modulation mode.
This bit determines which type of level transition on the ICAP1 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
OCIE
TOIE
FOLV2
Read/write
FOLV1
OLVL2
IEDG1
On-chip peripherals
OLVL1
0
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