st72324bk STMicroelectronics, st72324bk Datasheet - Page 64

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st72324bk

Manufacturer Part Number
st72324bk
Description
3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
Manufacturer
STMicroelectronics
Datasheet

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On-chip peripherals
Caution:
64/167
Table 34.
Bit 1 = OIE Oscillator interrupt enable
Bit 0 = OIF Oscillator interrupt flag
The BRES and BSET instructions must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
MCC beep control register (MCCBCR)
Reset Value: 0000 0000 (00h)
Bit 7:2 = Reserved, must be kept cleared.
Bit 1:0 = BC[1:0] Beep control
Table 35.
16000
32000
80000
200000
Counter prescaler
A modification of the time base is taken into account at the end of the current period
(previously set) to avoid an unwanted time shift. This allows to use this time base as a
real-time clock.
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from Active-Halt mode.
When this bit is set, calling the ST7 software Halt instruction enters the Active-Halt
power saving mode
This bit is set by hardware and cleared by software reading the MCCSR register. It
indicates when set that the main oscillator has reached the selected elapsed time
(TB1:0).
0: Timeout not reached
1: Timeout reached
These 2 bits select the PF1 pin beep capability.
7
0
BC1
0
Time base selection
Selecting the PF1 pin peep capability
0
4 ms
8 ms
20 ms
50 ms
BC0
0
..
f
OSC2
0
= 4 MHz
Time base
0
Read/Write
2 ms
4 ms
10 ms
25 ms
Beep mode with f
f
OSC2
0
= 8 MHz
Off
0
OSC2
= 8 MHz
0
0
1
1
ST72323 ST72323L
TB1
BC1
0
1
0
1
TB0
BC0
0

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