st72324bk STMicroelectronics, st72324bk Datasheet - Page 89

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

ST72323 ST72323L
Figure 44. Serial peripheral interface block diagram
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see
slave must be programmed with the same timing mode.
MOSI
MISO
SCK
SS
–
SS: Slave select:
This input signal acts as a ‘chip select’ to let the SPI master communicate with
slaves individually and to avoid contention on the data lines. Slave SS inputs can
be driven by standard I/O ports on the master MCU.
SOD
bit
Figure
SPIDR
45.
8-bit shift register
Read buffer
Serial clock
generator
Master
control
Data/address bus
Read
Write
7
SPIE SPE
SPIF WCOL
7
OVR
SPR2
control
state
SPI
Interrupt
request
Figure
MODF
MSTR
On-chip peripherals
CPOL
0
48) but master and
CPHA
SOD
SS
SPICR
SPICSR
SSM
SPR1
0
1
SPR0
SSI
89/167
0
0