st72324bk STMicroelectronics, st72324bk Datasheet - Page 79

• Manufacturer Part Number: st72324bk
• Description: 3 V/5 V Range 8-bit Mcu With 4/8 Kbyte Rom, 10-bit Adc, Four Timers And Spi
• Manufacturer: STMicroelectronics

ST72323 ST72323L
Note:
1
2
3
4
5
Figure 43. Pulse width modulation cycle
If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OC
the following formula:
Where:
●
●
●
If the timer clock is an external clock the formula is:
Where:
●
●
The Output Compare 2 event causes the counter to be initialized to FFFCh (See
After a write instruction to the OCiHR register, the output compare function is inhibited until
the OCiLR register is also written.
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
t = Signal or pulse period (in seconds)
f
PRESC
t = Signal or pulse period (in seconds)
f
CPU
EXT
i
R register value required for a specific timing application can be calculated using
= External timer clock frequency (in hertz)
= CPU clock frequency (in hertz)
= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see
OCiR = t
*
f
EXT
-5
Counter
= OC1R
Counter
= OC2R
When
When
OCiR Value =
Pulse width modulation cycle
OCMP1 = OLVL2
PRESC
t
OCMP1 = OLVL1
Counter is reset
*
ICF1 bit is set
f
CPU
to FFFCh
- 5
On-chip peripherals
Table
Figure
42)
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42)