AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 870

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

40.7
40.8
These timings are given for worst case process, T = 85°C, VDDCORE = 1.65V, VDDIO = 3V and 50 pF load capacitance.
Table 40-14. SMC Clock Signal.
Note:
Table 40-15. SMC Read Signals with Hold Settings
Note:
32054F–AVR32–09/09
Symbol
1/(t
Symbol
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
SMC
CPSMC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
AC Characteristics
EBI Timings
1. The maximum frequenzy of the SMC interface is the same as the max frequnzy for the HSB.
1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold length”.
)
Parameter
Data Setup before NRD High
Data Hold after NRD High
NRD High to NBS0/A0 Change
NRD High to NBS1 Change
NRD High to NBS2/A1 Change
NRD High to NBS3 Change
NRD High to A2 - A25 Change
NRD High to NCS Inactive
NRD Pulse Width
Data Setup before NCS High
Data Hold after NCS High
NCS High to NBS0/A0 Change
NCS High to NBS0/A0 Change
NCS High to NBS2/A1 Change
NCS High to NBS3 Change
NCS High to A2 - A25 Change
NCS High to NRD Inactive
NCS Pulse Width
Parameter
SMC Controller Clock Frequency
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
NRD Controlled (READ_MODE = 1)
NRD Controlled (READ_MODE = 0)
(nrd hold length - ncs rd hold length) * t
ncs rd hold length - nrd hold length)* t
ncs rd pulse length * t
ncs rd hold length * t
ncs rd hold length * t
ncs rd hold length * t
ncs rd hold length * t
ncs rd hold length * t
nrd pulse length * t
nrd hold length * t
nrd hold length * t
nrd hold length * t
nrd hold length * t
nrd hold length * t
11.2
12.4
Min
0
0
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
CPSMC
-
-
-
-
-
-
1.3
1.3
1.3
1.3
1.3
-
-
-
-
-
0.1
-
2.5
2.5
2.5
2.5
1.2
1.5
CPSMC
CPSMC
AT32AP7002
1/(2t
Max
-
-
cpcpu
4.3
0.6
(1)
)
Units
MHz
Units
ns
ns
870