AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 514

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

27.6.8
27.6.8.1
Figure 27-32. Read and Write Cycles in Slow Clock Mode
32054F–AVR32–09/09
NBS0, NBS1,
A0, A1
CLK_SMC
A[25:2]
NWE
NCS
Slow Clock Mode
Slow clock mode waveforms
SLOW CLOCK MODE WRITE
1
NWECYCLES = 3
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when
an internal signal driven by the SMC’s Power Management Controller is asserted because
CLK_SMC has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode,
the user-programmed waveforms are ignored and the slow clock mode waveforms are applied.
This mode is provided so as to avoid reprogramming the User Interface with appropriate wave-
forms at very slow clock rate. When activated, the slow mode is active on all chip selects.
Figure 27-32 on page 514
valid on all chip selects.
ters in slow clock mode.
Table 27-4.
Read Parameters
NRDSETUP
NRDPULSE
NCSRDSETUP
NCSRDPULSE
NRDCYCLE
1
Read and Write Timing Parameters in Slow Clock Mode
1
Duration (cycles)
Table 27-4 on page 514
illustrates the read and write operations in slow clock mode. They are
1
1
0
2
2
Write Parameters
NWESETUP
NWEPULSE
NCSWRSETUP
NCSWRPULSE
NWECYCLE
NBS0, NBS1,
indicates the value of read and write parame-
A0, A1
CLK_SMC
A[25:2]
NRD
NCS
SLOW CLOCK MODE READ
NRDCYCLES = 2
1
Duration (cycles)
AT32AP7002
1
1
0
3
3
1
514