AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 850

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

37.6.4
37.6.5
37.7
37.7.1
32054F–AVR32–09/09
Private JTAG Instructions
CLAMP
BYPASS
Notation
The active states are:
• Capture-DR: Data from the internal logic is sampled into the Boundary-Scan Chain.
• Shift-DR: The Internal Scan Chain is shifted by the TCK input.
• Update-DR: Data from the scan chain is applied to internal logic inputs.
This instruction selects the Bypass register as Data Register. The device output pins are driven
from the Boundary-Scan Chain.
The active states are:
• Capture-DR: Loads a logic ‘0’ into the Bypass Register.
• Shift-DR: Data is scanned from TDI to TDO through the Bypass register.
The active states are:
• Capture-DR: Loads a logic ‘0’ into the Bypass Register.
• Shift-DR: Data is scanned from TDI to TDO through the Bypass register.
The AVR32 defines a number of private JTAG instructions. Each instruction is briefly described
in text, with details following in table form.
Table 37-4 on page 851
corresponds to one bit, and eight bits are grouped together for readability. The rightmost bit is
always shifted first, and the leftmost bit shifted last. The symbols used are shown in
Table 37-3.
JTAG instruction selecting the 1-bit Bypass Register for Data Register.
Symbol
0
1
a
b
d
e
p
x
r
Description
Constant low value - always reads as zero.
Constant high value - always reads as one.
An address bit - always scanned with the least significant bit first
A busy bit. Reads as one if the SAB was busy, or zero if it was not. See
page 847
A data bit - always scanned with the least significant bit first.
An error bit. Reads as one if an error occurred, or zero if not. See
847
The chip protected bit. Some devices may be set in a protected state where access to chip
internals are severely restricted. See the documentation for the specific device for details.
On devices without this possibility, this bit always reads as zero.
A direction bit. Set to one to request a read, set to zero to request a write.
A don’t care bit. Any value can be shifted in, and output data should be ignored.
Symbol description
for details on how the error reporting works.
for details on how the busy reporting works.
shows bit patterns to be shifted in a format like "peb01". Each character
AT32AP7002
”Error reporting” on page
”Busy reporting” on
Table
37-3.
850