AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 357

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

23.7.8
23.7.9
32054F–AVR32–09/09
Loop Mode
Interrupt
Figure 23-14. Transmit Frame Format in Continuous Mode
Note:
Figure 23-15. Receive Frame Format in Continuous Mode
Note:
The receiver can be programmed to receive transmissions from the transmitter. This is done by
setting the Loop Mode (LOOP) bit in RFMR. In this case, RX_DATA is connected to TX_DATA,
RX_FRAME_SYNC is connected to TX_FRAME_SYNC and RX_CLOCK is connected to
TX_CLOCK.
Most bits in SR have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is
controlled by writing IER (Interrupt Enable Register) and IDR (Interrupt Disable Register) These
registers enable and disable, respectively, the corresponding interrupt by setting and clearing
the corresponding bit in IMR (Interrupt Mask Register), which controls the generation of inter-
rupts by asserting the SSC interrupt line connected to the interrupt controller.
1. STTDLY is set to 0. In this example, THR is loaded twice. FSDEN value has no effect on the
1. STTDLY is set to 0.
transmission. SyncData cannot be output in continuous mode.
TX_DATA
Start: 1. TXEMPTY set to 1
RX_DATA
2. Write into the THR
Start
From THR
DATLEN
Start = Enable Receiver
Data
DATLEN
To RHR
Data
From THR
DATLEN
Data
DATLEN
To RHR
Data
Default
AT32AP7002
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