AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 203

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

• DMS: Destination Master Select
Identifies the Master Interface layer where the destination device (peripheral or memory) resides
Table 17-5.
• TT_FC: Transfer Type and Flow Control
The four following transfer types are supported:
• Memory to Memory, Memory to Peripheral, Peripheral to Memory and Peripheral to Peripheral.
The DMACA is always the Flow Controller.
• DST_SCATTER_EN: Destination Scatter Enable
Scatter on the destination side is applicable only when the CTLx.DINC bit indicates an incrementing or decrementing
address control.
• SRC_GATHER_EN: Source Gather Enable
Gather on the source side is applicable only when the CTLx.SINC bit indicates an incrementing or decrementing address
control.
• SRC_MSIZE: Source Burst Transaction Length
Number of data items, each of width CTLx.SRC_TR_WIDTH, to be read from the source every time a source burst transac-
tion request is made from either the corresponding hardware or software handshaking interface.
32054F–AVR32–09/09
DMS
0
1
Other
TT_FC
000
001
010
011
Other
SRC_MSIZE
0
1
2
0 = Scatter disabled
1 = Scatter enabled
Important note: This bit is only implemented for channel 1, not for channels 0 and 2.
0 = Gather disabled
1 = Gather enabled
Important note: This bit is only implemented for channel 1, not for channels 0 and 2.
Destination Master Select
HSB Master
HSB master 1
HSB master 2
Reserved
Transfer Type
Memory to Memory
Memory to Peripheral
Peripheral to Memory
Peripheral to Peripheral
Reserved
Size (items number)
1
4
8
Flow Controller
DMACA
DMACA
DMACA
DMACA
Reserved
AT32AP7002
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