AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 632

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

31.7.4
Name:
Access Type:
• SPEED: Speed Status
0 = reset by hardware when the hardware is in Full Speed mode.
1 = set by hardware when the hardware is in High Speed mode
• DET_SUSPD: Suspend Interrupt
0 = cleared by setting the DET_SUSPD bit in CLRINT register
1 = set by hardware when a USBA Suspend (Idle bus for three frame periods, a J state for 3 ms) is detected. This triggers
a USBA interrupt when the DET_SUSPD bit is set in IEN register.
• MICRO_SOF: Micro Start Of Frame Interrupt
0 = cleared by setting the MICRO_SOF bit in CLRINT register.
1 = set by hardware when an USBA micro start of frame PID (SOF) has been detected (every 125 us) or synthesized by the
macro. This triggers a USBA interrupt when the MICRO_SOF bit is set in IEN. In case of detected SOF, the
MICRO_FRAME_NUM field in FNUM register is incremented and the FRAME_NUMBER field doesn’t change.
Note:
• INT_SOF: Start Of Frame Interrupt
0 = cleared by setting the INT_SOF bit in CLRINT.
1 = set by hardware when an USBA Start Of Frame PID (SOF) has been detected (every 1 ms) or synthesized by the
macro. This triggers a USBA interrupt when the INT_SOF bit is set in IEN register. In case of detected SOF, in High Speed
mode, the MICRO_FRAME_NUMBER field is cleared in FNUM register and the FRAME_NUMBER field is updated.
• ENDRESET: End Of Reset Interrupt
0 = cleared by setting the ENDRESET bit in CLRINT.
1 = set by hardware when an End Of Reset has been detected by the USBA controller. This triggers a USBA interrupt when
the ENDRESET bit is set in IEN.
32054F–AVR32–09/09
UPSTR_RES
EPT_INT_7
31
23
15
7
The Micro Start Of Frame Interrupt (MICRO_SOF), and the Start Of Frame Interrupt (INT_SOF) are not generated at the same
time.
USBA Interrupt Status Register
ENDOFRSM
DMA_INT_6
EPT_INT_6
30
22
14
6
DMA_INT_5
EPT_INT_5
WAKE_UP
29
21
13
5
INTSTA
Read-only
DMA_INT_4
ENDRESET
EPT_INT_4
28
20
12
4
DMA_INT_3
EPT_INT_3
INT_SOF
27
19
11
3
MICRO_SOF
DMA_INT_2
EPT_INT_2
26
18
10
2
DET_SUSPD
DMA_INT_1
EPT_INT_1
AT32AP7002
25
17
9
1
EPT_INT_0
SPEED
24
16
–
8
0
632