AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 453

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

25.7.5.5
25.7.5.6
25.7.5.7
32054F–AVR32–09/09
AC97 Codec Reset
Cold AC97 Reset
Warm AC97 Reset
There are three ways to reset an AC97 Codec.
A cold reset is generated by asserting the RESET signal low for the minimum specified time
(depending on the AC97 Codec) and then by de-asserting RESET high. BITCLK and SYNC is
reactivated and all AC97 Codec registers are set to their default power-on values. Transfers on
AC-link can resume.
The RESET signal will be controlled via a PIO line. This is how an application should perform a
cold reset:
BITCLK, the clock provided by AC97 Codec, is detected by the controller.
A warm reset reactivates the AC-link without altering AC97 Codec registers. A warm reset is sig-
naled by driving AC97FX signal high for a minimum of 1us in the absence of BITCLK. In the
absence of BITCLK, AC97FX is treated as an asynchronous (regarding AC97FX) input used to
signal a warm reset to AC97 Codec.
This is the right way to perform a warm reset:
The application can check that operations have resumed by checking SOF flag in the SR regis-
ter or wait for an interrupt notice if SOF is enabled in IMR.
•Clear and set ENA flag in the MR register to reset the AC97 Controller
•Clear PIO line output controlling the AC97 RESET signal
•Wait for the minimum specified time
•Set PIO line output controlling the AC97 RESET signal
•Set WRST in the MR register.
•Wait for at least 1us
•Clear WRST in the MR register.
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