AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 103

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

10.5.7
10.5.7.1
32054F–AVR32–09/09
Generic clocks
Enabling a generic clock
NEXUS_ACCESS or a MEMORY_ACCESS JTAG command is loaded into the instruction regis-
ter before entering sleep mode some clocks are left running to enable debugging of the system.
This will increase the power consumption of the device. If the part entered static mode without a
NEXUS_ACCESS ot MEMORY_ACCESS instruction loaded into the JTAG instruction register
an external reset is the only way for the debugger to get the part out of the sleep mode.
When not debugging a program and using sleep modes the JTAG should always have the
IDCODE instruction loaded into the JTAG instruction register and the OCD system should be
disabled. Otherwise some clocks may be left running, increasing the power consumption.
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The Power Manager contains an implementation
defined number of generic clocks, that can provide a wide range of accurate clock frequencies.
Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source
can optionally be divided by any even integer up to 512. Each clock can be independently
enabled and disabled, and is also automatically disabled along with peripheral clocks by the
Sleep Controller.
Figure 10-4. Generic clock generation
A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use
either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits.
The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV,
resulting in the output frequency:
Osc0 clock
Osc1 clock
PLL0 clock
PLL1 clock
f
GCLK
= f
SRC
OSCSEL
PLLSEL
/
(2*(DIV+1))
0
1
Divider
DIV
DIVEN
0
1
Controller
Sleep
Mask
CEN
AT32AP7002
Generic Clock
103