AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 135
AT32AP7002-CTUT
Manufacturer Part Number
AT32AP7002-CTUT
Description
IC MCU 32BIT AVR32 196-CBGA
Manufacturer
Atmel
Series
AVR®32 AP7r
Specifications of AT32AP7002-CTUT
Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, LCD, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
196-CBGA
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
Maximum Clock Frequency
150 MHz
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 2 Channel
Package
196CTBGA
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
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14. External Interrupt Controller (EIC)
14.1
14.2
14.3
Figure 14-1. External Interrupt Controller block diagram
14.4
14.4.1
32054F–AVR32–09/09
EXTINTn
NMI_N
Features
Description
Block Diagram
Product Dependencies
I/O Lines
Rev: 1.0.0.1
•
•
•
•
•
The External Interrupt Controller allows 4 pins to be configured as external interrupts. Each pin
has its own interrupt request, and can be individually masked. Each pin can generate an inter-
rupt on rising or falling edge, or high or low level.
The module also masks the NMI_N pin, which generates the NMI interrupt for the CPU.
The External Interrupt and NMI pins are multiplexed with PIO lines. To act as external interrupts,
these pins must be configured as inputs pins by the PIO controller. It is also possible to trigger
the interrupt by driving these pins from registers in the PIO controller, or another peripheral out-
put connected to the same pin.
Dedicated interrupt requests for each interrupt
Individually maskable interrupts
Interrupt on rising or falling edge
Interrupt on high or low level
Maskable NMI interrupt
Sync
Sync
Edge/Level
Mask
Detector
NMIC
LEVEL
MODE
NMI_IRQ
INTn
ICR
ISR
AT32AP7002
Mask
IMR
IER
IDR
IRQn
135
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