AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 333

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

CLOCK
DATA
22.4.2
32054F–AVR32–09/09
Host to device communication
• 1 start bit - always 0.
• 8 data bits, least significant bit first.
• 1 parity bit - odd parity.
• 1 stop bit - always 1.
Figure 22-1. Device to host transfer
Because the device always generates the clock, host to device communication is done differ-
ently than device to host communication.
• The host starts by inhibiting communication by pulling clock low for a minimum of 100
• Then applies a “request-to-send” by releasing clock and pulling data low.
The device must check for this state at least every 10 milliseconds. Once it detects a request-to-
send, it must start generating the clock and receive one frame of data. The host writes a data bit
when the clock is low, and the device reads the bit when the clock is high.
The format of the frame is:
• 1 start bit - always 0.
• 8 data bits - least significant bit first.
• 1 parity bit - odd parity
• 1 stop bit - always one.
• 1 acknowledge bit - the device acknowledges by pulling data low.
microseconds.
AT32AP7002
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