AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 184

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

32054F–AVR32–09/09
4. After the DMACA selected channel has been programmed, enable the channel by writing
5. Source and destination request single and burst DMACA transactions to transfer the
6. When the block transfer has completed, the DMACA reloads the SARx, DARx and CTLx
7. The DMA transfer proceeds as follows:
a. Write the starting source address in the SARx register for channel x.
b. Write the starting destination address in the DARx register for channel x.
c. Program CTLx and CFGx according to Row 4 as shown in
d. Write the control information for the DMA transfer in the CTLx register for channel x.
– i. Set up the transfer type (memory or non-memory peripheral for source and
– ii. Set up the transfer characteristics, such as:
e. Write the channel configuration information into the CFGx register for channel x.
– i. Designate the handshaking interface type (hardware or software) for the source and
– ii. If the hardware handshaking interface is activated for the source or destination
a ‘1’ to the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgReg register is
enabled.
block of data (assuming non-memory peripherals). The DMACA acknowledges on com-
pletion of each burst/single transaction and carry out the block transfer.
registers. Hardware sets the Block Complete interrupt. The DMACA then samples the
row number as shown in
DMA transfer has completed. Hardware sets the transfer complete interrupt and disables
the channel. So you can either respond to the Block Complete or Transfer Complete
interrupts, or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is disabled, to
detect when the transfer is complete. If the DMACA is not in Row 1, the next step is
performed.
a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is un-
destination) and flow control device by programming the TT_FC of the CTLx register.
destination peripherals. This is not required for memory. This step requires
programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination requests
for the specific channel. Writing a ‘1’ activates the software handshaking interface to
handle source/destination requests.
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DEST_PER bits, respectively.
Program the LLPx register with ‘0’.
For example, in the register, you can program the following:
Ensure that the reload bits, CFGx. RELOAD_SR and CFGx.RELOAD_DS are
enabled.
masked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the
block complete interrupt when the block transfer has completed. It then stalls until the
block complete interrupt is cleared by software. If the next block is to be the last block
in the DMA transfer, then the block complete ISR (interrupt service routine) should
– Transfer width for the source in the SRC_TR_WIDTH field.
– Transfer width for the destination in the DST_TR_WIDTH field.
– Source master layer in the SMS field where source resides.
– Destination master layer in the DMS field where destination resides.
– Incrementing/decrementing or fixed address for source in SINC field.
– Incrementing/decrementing or fixed address for destination in DINC field.
Table 17-1 on page
176. If the DMACA is in Row 1, then the
Table 17-1 on page
AT32AP7002
176.
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