AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 544

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

28.8.3
Register Name:
Access Type:
Offset:
Reset Value:
• TXSR: Exit Self Refresh to Active Delay
• TRAS: Active to Precharge Delay
• TRCD: Row to Column Delay
• TRP: Row Precharge Delay
• TRC: Row Cycle Delay
• TWR: Write Recovery Delay
• DBW: Data Bus Width
32054F–AVR32–09/09
DBW
31
23
15
7
Reset value is eight cycles.
This field defines the delay between SCKE set high and an Activate command in number of cycles. Number of cycles is between
0 and 15.
Reset value is five cycles.
This field defines the delay between an Activate command and a Precharge command in number of cycles. Number of cycles is
between 0 and 15.
Reset value is two cycles.
This field defines the delay between an Activate command and a Read/Write command in number of cycles. Number of cycles
is between 0 and 15.
Reset value is three cycles.
This field defines the delay between a Precharge command and another command in number of cycles. Number of cycles is
between 0 and 15.
Reset value is seven cycles.
This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is between 0
and 15.
Reset value is two cycles.
This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15.
Reset value is 16 bits.
0: Data bus width is 32 bits.
1: Data bus width is 16 bits.
Configuration Register
30
22
14
6
CR
Read/Write
0x08
0x852372C0
TRCD
TXSR
TRC
CAS
29
21
13
5
NB
28
20
12
4
27
19
11
3
NR
26
18
10
2
TRAS
TWR
TRP
25
17
9
1
AT32AP7002
NC
24
16
8
0
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