AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 732

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

33.7.12
Register Name:
Access Type:
Only the first 20 bits (internal channel counter size) are significant.
•
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
32054F–AVR32–09/09
CPRD: Channel Period
31
23
15
7
PWM Channel Period Register
30
22
14
6
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula
1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
becomes, respectively:
1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
becomes, respectively:
(
------------------------------ -
(
----------------------------------------- -
(
---------------------------------------- -
(
--------------------------------------------------- -
X CPRD
CRPD
2
2
×
×
×
MCK
X CPRD
CPRD DIVA
29
21
13
MCK
5
MCK
CPRDx
Read/Write
×
MCK
×
DIVA
)
×
)
)
or
)
(
--------------------------------------------- -
or
CRPD
28
20
12
4
(
--------------------------------------------------- -
2 CPRD
MCK
×
CPRD
CPRD
CPRD
CPRD
×
DIVAB
MCK
×
)
DIVB
27
19
11
3
)
26
18
10
2
AT32AP7002
25
17
9
1
24
16
8
0
732