AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 619
AT32AP7002-CTUT
Manufacturer Part Number
AT32AP7002-CTUT
Description
IC MCU 32BIT AVR32 196-CBGA
Manufacturer
Atmel
Series
AVR®32 AP7r
Specifications of AT32AP7002-CTUT
Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, LCD, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
196-CBGA
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
Maximum Clock Frequency
150 MHz
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 2 Channel
Package
196CTBGA
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
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31.6.7
31.6.8
31.6.9
32054F–AVR32–09/09
Speed Identification
USB V2.0 High Speed Global Interrupt
Endpoint Interrupts
The high speed reset is managed by the hardware.
At the connection, the host makes a reset which could be a classic reset (full speed) or a high
speed reset.
At the end of the reset process (full or high), the ENDRESET interrupt is generated.
Then the CPU should read the SPEED bit in INTSTAx to ascertain the speed mode of the
device.
Interrupts are defined in
31.7.4 ”USBA Interrupt Status Register”
Interrupts are enabled in IEN (see
ually masked in EPTCTLENBx (see
Table 31-5.
SHRT_PCKT
BUSY_BANK
NAK_OUT
NAK_IN/ERR_FLUSH
STALL_SNT/ERR_CRISO/ERR_NB_TRA
RX_SETUP/ERR_FL_ISO
TX_PK_RD /ERR_TRANS
TX_COMPLT
RX_BK_RDY
ERR_OVFLW
MDATA_RX
DATAX_RX
Endpoint Interrupt Source Masks
Section 31.7.3 ”USBA Interrupt Enable Register”
Section 31.7.3 ”USBA Interrupt Enable
Section 31.7.18 ”USBA Endpoint Control Enable
(INTSTA).
Short Packet Interrupt
Busy Bank Interrupt
NAKIN/Error Flush Interrupt
Transmitted IN Data Complete Interrupt
Overflow Error Interrupt
MDATA Interrupt
DATAx Interrupt
NAKOUT Interrupt
Stall Sent/CRC error/Number of Transaction Error Interrupt
Received SETUP/Error Flow Interrupt
TX Packet Read/Transaction Error Interrupt
Received OUT Data Interrupt
AT32AP7002
Register”) and individ-
(IEN) and in
Register”).
Section
619
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