AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 547
AT32AP7002-CTUT
Manufacturer Part Number
AT32AP7002-CTUT
Description
IC MCU 32BIT AVR32 196-CBGA
Manufacturer
Atmel
Series
AVR®32 AP7r
Specifications of AT32AP7002-CTUT
Core Processor
AVR
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²C, LCD, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
D/A 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
196-CBGA
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
Maximum Clock Frequency
150 MHz
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Dac
16 bit, 2 Channel
Package
196CTBGA
Device Core
AVR32
Family Name
AT32
Maximum Speed
150 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
Quantity
Price
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28.8.5
Register Name:
Access Type:
Offset:
Reset Value:
• TIMEOUT: Time to Define when Low Power Mode Is Enabled
• DS: Drive Strength (only for low power SDRAM)
• TCSR: Temperature Compensated Self Refresh (only for low power SDRAM)
• PASR: Partial Array Self Refresh (only for low power SDRAM)
32054F–AVR32–09/09
TIMEOUT
31
23
15
7
-
-
-
-
0
1
2
3
This field is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parameter must be
set according to the SDRAM device specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatically and its DS parameter value is updated before entry in self refresh mode.
This field is transmitted to the SDRAM during initialization to set the refresh interval during self refresh mode depending on the
temperature of the low power SDRAM. This parameter must be set according to the SDRAM device specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatically and its TCSR parameter value is updated before entry in self refresh mode.
This field is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks of the
SDRAM array are enabled. Disabled banks are not refreshed in self refresh mode. This parameter must be set according to the
SDRAM device specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatically and its PASR parameter value is updated before entry in self refresh mode.
Low Power Register
Time to Define when Low Power Mode Is Enabled
The SDRAMC activates the SDRAM low power mode immediately after the end of the last transfer.
The SDRAMC activates the SDRAM low power mode 64 clock cycles after the end of the last transfer.
The SDRAMC activates the SDRAM low power mode 128 clock cycles after the end of the last transfer.
Reserved.
30
22
14
6
-
-
-
LPR
Read/Write
0x10
0x00000000
PASR
29
21
13
5
-
-
TIMEOUT
28
20
12
4
-
-
27
19
11
3
-
-
-
DS
26
18
10
2
-
-
-
25
17
9
1
-
-
AT32AP7002
TCSR
LPCB
24
16
8
0
-
-
547
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