AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 748

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

32054F–AVR32–09/09
Figure 34-3. Full Frame Timing, MMODE=1, MVAL=1
Figure 34-4. Full Frame Timing, MMODE=0
The PCLK signal is used to clock the data into the LCD drivers' shift register. The data is sent
through LCDD[23:0] synchronized by default with the PCLK falling edge (rising edge can be
selected). The CLKVAL field of LCDCON1 register controls the rate of this signal. The divisor
can also be bypassed with the BYPASS bit in the LCDCON1 register. In this case, the rate of
PCLK is equal to the frequency of the LCDC Core Clock. The minimum period of the PCLK sig-
nal depends on the configuration. This information can be found in
The PCLK signal has two different timings that are selected with the CLKMOD field of the
LCDCON2 register:
Table 34-11. Minimum PCLK Period in LCDC Core Clock Cycles
DISTYPE
TFT
STN Mono
STN Mono
STN Mono
STN Mono
STN Color
•Always Active (used with TFT LCD Modules)
•Active only when data is available (used with STN LCD Modules)
f
LCD_PCLK
LCD_PCLK
LCD_PCLK
LCD_MODE
LCD_MODE
LCD_VSYNC
LCD_VSYNC
SCAN
Single
Single
Dual
Dual
Single
=
------------------------------- -
2
f
Configuration
LCDC_clock
×
Line1
Line1
CLKVAL
Line2
Line2
Line3
Line3
Line4
Line4
Line5
Line5
IFWIDTH
16
4
4
8
8
Table
AT32AP7002
34-11.
PCLK Period
1
4
8
8
16
2
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