AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 503

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

27.6.5.3
32054F–AVR32–09/09
Reload user configuration wait state
•User procedure
Figure 27-20. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read
The user may change any of the configuration parameters by writing the SMC user interface.
When detecting that a new user configuration has been written in the user interface, the SMC
inserts a wait state before starting the next access. The so called “reload user configuration wait
state” is used by the SMC to load the new set of parameters to apply to next accesses.
The reload configuration wait state is not applied in addition to the chip select wait state. If
accesses before and after reprogramming the user interface are made to different devices (dif-
ferent chip selects), then one single chip select wait state is applied.
On the other hand, if accesses before and after writing the user interface are made to the same
device, a reload configuration wait state is inserted, even if the change does not concern the cur-
rent chip select.
To insert a reload configuration wait state, the SMC detects a write access to any MODE register
of the user interface. If the user only modifies timing registers (SETUP, PULSE, CYCLE regis-
ters) in the user interface, he must validate the modification by writing the MODE register, even
if no change was made on the mode parameters.
Internal write controlling signal
external write controlling
signal(NWE)
with one Set-up Cycle.
NBS0, NBS1,
A0, A1
D[15:0]
CLK_SMC
A[25:2]
NRD
(WRITEMODE = 1)
Write cycle
No hold
Early Read
Wait State
Read setup=1
(READMODE=0 or READMODE=1)
AT32AP7002
Read cycle
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