AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 522

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

27.7.3
Register Name:
Access Type:
Offset:
Reset Value:
• NRDCYCLE[8:0]: Total Read Cycle Length
• NWECYCLE[8:0]: Total Write Cycle Length
32054F–AVR32–09/09
31
23
15
–
–
7
The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and
hold steps of the NRD and NCS signals. It is defined as:
The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and
hold steps of the NWE and NCS signals. It is defined as:
Cycle Register
30
22
14
6
–
–
CYCLE
Read/Write
0x08 + CS_number*0x10
0x00030003
Write Cycle Length
Read Cycle Length
29
21
13
–
–
5
=
=
(
(
256 NWECYCLE 8:7
256 NRDCYCLE 8:7
×
×
28
20
12
4
–
–
NWECYCLE[7:0]
NRDCYCLE[7:0]
[
[
]
]
27
19
11
–
–
3
+
+
NRDCYCLE 6:0
NWECYCLE 6:0
[
[
26
18
10
2
–
–
]
]
) clock cycles
) clock cycles
25
17
–
9
–
1
AT32AP7002
NWECYCLE[8]
NRDCYCLE[8]
24
16
8
0
522