AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 187

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

32054F–AVR32–09/09
3. Write the starting source address in the SARx register for channel x.
Note:
4. Write the channel configuration information into the CFGx register for channel x.
5. Make sure that the LLI.CTLx register locations of all LLIs in memory (except the last) are
6. Make sure that the LLI.LLPx register locations of all LLIs in memory (except the last) are
7. Make sure that the LLI.DARx register location of all LLIs in memory point to the start des-
8. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLIs in
9. Clear any pending interrupts on the channel from the previous DMA transfer by writing to
10. Program the CTLx, CFGx registers according to Row 7 as shown in
11. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.
12. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is
13. The DMACA fetches the first LLI from the location pointed to by LLPx(0).
Note:
14. Source and destination request single and burst DMACA transactions to transfer the
15.
16. The DMA transfer proceeds as follows:
a. Designate the handshaking interface type (hardware or software) for the source and
b. If the hardware handshaking interface is activated for the source or destination
set as shown in Row 7 of
Linked List item must be set as described in Row 1 or Row 5 of
Figure 17-7 on page 175
non-zero and point to the next Linked List Item.
tination block address proceeding that LLI fetch.
memory is cleared.
the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr.
Reading the Interrupt Raw Status and Interrupt Status registers confirms that all inter-
rupts have been cleared.
176.
performed. Make sure that bit 0 of the DmaCfgReg register is enabled.
block of data (assuming non-memory peripherals). DMACA acknowledges at the comple-
tion of every transaction (burst and single) in the block and carry out the block transfer.
Table 17-1 on page
Hardware sets the block complete interrupt. The DMACA samples the row number as
shown in
has completed. Hardware sets the transfer complete interrupt and disables the channel.
You can either respond to the Block Complete or Transfer Complete interrupts, or poll for
the Channel Enable (ChEnReg.CH_EN) bit until it is cleared by hardware, to detect when
the transfer is complete. If the DMACA is not in Row 1 or 5 as shown in
page 176
a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is un-
The values in the LLI.SARx register locations of each of the Linked List Items (LLIs) setup up in
memory, although fetched during a LLI fetch, are not used.
destination peripherals. This is not required for memory. This step requires program-
ming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ activates the
hardware handshaking interface to handle source/destination requests for the spe-
cific channel. Writing a ‘1’ activates the software handshaking interface
source/destination requests.
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_PER and DEST_PER bits, respectively.
The LLI.SARx, LLI.DARx, LLI. LLPx and LLI.CTLx registers are fetched. The LLI.SARx register
although fetched is not used.
masked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the
block complete interrupt when the block transfer has completed. It then stalls until the
Table 17-1 on page
the following steps are performed.
176The DMACA reloads the SARx register from the initial value.
shows a Linked List example with two list items.
Table 17-1 on page 176
176. If the DMACA is in Row 1 or 5, then the DMA transfer
while the LLI.CTLx register of the last
Table 17-1 on page
AT32AP7002
Table 17-1 on page
Table 17-1 on
176.
187