AT32AP7002-CTUT Atmel, AT32AP7002-CTUT Datasheet - Page 180

• Manufacturer Part Number: AT32AP7002-CTUT
• Description: IC MCU 32BIT AVR32 196-CBGA
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7002-CTUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, LCD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-CBGA
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, JTAG, PS2, SPI, SSC, UART, USART, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 2 Channel
• Package: 196CTBGA
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8|3.3 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

32054F–AVR32–09/09
4. Make sure that the LLI.CTLx register locations of all LLI entries in memory (except the
5. Make sure that the LLI.LLPx register locations of all LLI entries in memory (except the
6. Make sure that the LLI.SARx/LLI.DARx register locations of all LLI entries in memory
7. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLI
8. Clear any pending interrupts on the channel from the previous DMA transfer by writing to
9. Program the CTLx, CFGx registers according to Row 10 as shown in
10. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.
11. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is
12. The DMACA fetches the first LLI from the location pointed to by LLPx(0).
Note:
13. Source and destination request single and burst DMA transactions to transfer the block of
Note:
14. The DMACA does not wait for the block interrupt to be cleared, but continues fetching the
b. If the hardware handshaking interface is activated for the source or destination
last) are set as shown in Row 10 of
last Linked List Item must be set as described in Row 1 or Row 5 of
176.
last) are non-zero and point to the base address of the next Linked List Item.
point to the start source/destination block address preceding that LLI fetch.
entries in memory are cleared.
the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr.
Reading the Interrupt Raw Status and Interrupt Status registers confirms that all inter-
rupts have been cleared.
176.
performed.
data (assuming non-memory peripheral). The DMACA acknowledges at the completion
of every transaction (burst and single) in the block and carry out the block transfer.
next LLI from the memory location pointed to by current LLPx register and automatically
reprograms the SARx, DARx, LLPx and CTLx channel registers. The DMA transfer con-
tinues until the DMACA determines that the CTLx and LLPx registers at the end of a
block transfer match that described in Row 1 or Row 5 of
DMACA then knows that the previous block transferred was the last block in the DMA
transfer. The DMA transfer might look like that shown in
ming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ activates the
hardware handshaking interface to handle source/destination requests for the spe-
cific channel. Writing a ‘1’ activates the software handshaking interface to handle
source/destination requests.
peripheral, assign the handshaking interface to the source and destination periph-
eral. This requires programming the SRC_PER and DEST_PER bits, respectively.
The LLI.SARx, LLI. DARx, LLI.LLPx and LLI.CTLx registers are fetched. The DMACA automati-
cally reprograms the SARx, DARx, LLPx and CTLx channel registers from the LLPx(0).
Table 17-1 on page 176
Figure 17-9 on page 182
shows a Linked List example with two list items.
Table 17-1 on page
176. The LLI.CTLx register of the
Figure 17-8 on page
Table 17-1 on page
AT32AP7002
Table 17-1 on page
Table 17-1 on page
181.
176. The
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